By Ali Hurson
Этот свежий сборник знакомит с последними достижениями в архитектуре компьютеров.
Register-Level verbal exchange in Speculative Chip Multiprocessors
Survey on procedure I/O Transactions and effect on Latency, Throughput, and different Factors
Hardware and alertness Profiling Tools
Model Transformation utilizing Multiobjective Optimization
Manual Parallelization as opposed to cutting-edge Parallelization ideas: The SPEC CPU2006 as a Case learn
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Additional resources for Advances in Computers, Volume 92
This figure is taken from  with permission from the copyright holder. 2 Architecture Details The block diagram of Mitosis is presented in Fig. 15. It consists of the TUs that are similar to conventional superscalar cores. Each TU has local multiversion register file (MRF) and multiversion cache, and they are connected to the global L2 cache via shared bus. The Speculation Engine handles the tasks related to the execution of the speculative thread: the allocation of free TU, the initialization of some registers, and maintaining the order among new and other active threads.
IACOMA uses a binary annotation tool to identify the units of work for each speculative thread and the register-level dependencies between them . Pinot relies on a profile-guided parallelizing tool to extract thread-level parallelism at any level of granularity from sequential binaries and to convert them into SM binaries . Finally, SM, Trace, and Atlas rely completely on hardware support to dynamically extract threads from sequential binaries [16,2,45]. A hardware mechanism for thread identification instead of software techniques has several advantages: (a) The compiler control flow analysis is less accurate; (b) the outcomes of data dependence profiling techniques used by compiler to enhance control flow analysis rely on concrete set of input data; (c) the use of data dependence profiling mechanisms incurs run time and memory overhead when profiling large and long-running applications; and (d) some software approaches require modification of instruction-set architecture, which does not provide backward compatibility with previous implementations.
3 Prediction of Register Values Parameters CMP Data Prediction Support Register Communication SM  Hardware-based scheme Good control and data predictability Severe load imbalance Coverage problems Producer-initiated Atlas  Hardware-based scheme Small threads Improved control predictability Consumer-initiated verification of predicted values Trace  Hardware-based scheme Good control and data predictability Severe load imbalance Coverage problems Producer-initiated verification of predicted values Mitosis  Software-based scheme Improved prediction accuracy Encapsulates multiple control flows Producer- and consumer-initiated much simpler than in Multiscalar, since each core has three extra local bits (X bits) per register only.
Advances in Computers, Volume 92 by Ali Hurson